凯发

Recent research advances at fabricating FETs with 2D semiconductors have inspired the industry to begin with integration of these new technologies into FAB process flows, thereby potentially making them interesting for advanced manufacturing areas. For instance, Intel already has 300mm FAB process for MoS2, WS2, WSe2 and MoSe2 at CMOS compatible temperatures and recently reported complementary integration of MoS2 n-type FETs and WSe2 p-type FETs. Imec has also demonstrated functional MoS2 and WS2 FETs produced using their 300mm FAB lines. However, the transition of new 2D technologies from research labs to FAB process lines is still very challenging due to a number of open questions, such as the need to satisfy CMOS thermal budget below 450oC, top-gate integration by growing 3D oxides on 2D channels and reliability limitations due to charge trapping near the channel/oxide or top gate/oxide interfaces.
In this talk I will summarize recent progress made by the industry at integrating 2D FETs into FAB lines, discuss the main challenges which arise on this way, and try to benchmark reliability limitations of first FAB 2D FETs based on our recent experimental results. I will also touch the related problems for 2D photodetectors which are still behind FETs on their way to advanced manufacturing applications, even though an enormous progress has been made at the prototype level.